Main Page | Modules | Data Structures | Directories | File List | Data Fields | Globals | Related Pages

# aic23b.h

Go to the documentation of this file.

    00001 /*! \file aic23b.h \brief TI TLV320AIC23B Audio Codec Driver. */
    00002 //*****************************************************************************
    00003 //
    00004 // File Name    : 'aic23b.h'
    00005 // Title        : TI TLV320AIC23B Audio Codec Driver
    00006 // Author       : Pascal Stang - Copyright (C) 2004
    00007 // Created      : 2004.05.05
    00008 // Revised      : 2004.07.12
    00009 // Version      : 0.1
    00010 // Target MCU   : ARM processors
    00011 // Editor Tabs  : 4
    00012 //
    00013 // NOTE: This code is currently below version 1.0, and therefore is considered
    00014 // to be lacking in some functionality or documentation, or may not be fully
    00015 // tested.  Nonetheless, you can expect most functions to work.
    00016 //
    00017 // This code is distributed under the GNU Public License
    00018 //      which can be found at http://www.gnu.org/licenses/gpl.txt
    00019 //
    00020 //*****************************************************************************
    00021
    00022
    00023 #ifndef AIC23B_H
    00024 #define AIC23B_H
    00025
    00026 #define AIC_I2C_ADDR                0x34
    00027
    00028 #define AIC_REG_VOL_LINEIN_LEFT     0x0000
    00029 #define AIC_REG_VOL_LINEIN_RIGHT    0x0200
    00030 #define AIC_REG_VOL_HP_LEFT         0x0400
    00031 #define AIC_REG_VOL_HP_RIGHT        0x0600
    00032 #define AIC_REG_ANALOG_PATH         0x0800
    00033 #define AIC_REG_DIGITAL_PATH        0x0A00
    00034 #define AIC_REG_POWERDOWN           0x0C00
    00035 #define AIC_REG_INTERFACE_FORMAT    0x0E00
    00036 #define AIC_REG_SAMPLE_RATE         0x1000
    00037 #define AIC_REG_DIGITAL_IF_ACT      0x1200
    00038 #define AIC_REG_RESET               0x1E00
    00039
    00040 // AIC_REG_VOL_LINEIN_LEFT bits
    00041 #define AIC_VLIL_LRS    8   // 0=disabled 1=left/right simultaneous update
    00042 #define AIC_VLIL_LIM    7   // 0=Normal 1=Muted
    00043 #define AIC_VLIL_LIV4   4
    00044 #define AIC_VLIL_LIV3   3
    00045 #define AIC_VLIL_LIV2   2
    00046 #define AIC_VLIL_LIV1   1
    00047 #define AIC_VLIL_LIV0   0
    00048
    00049 // AIC_REG_VOL_LINEIN_RIGHT bits
    00050 #define AIC_VLIR_RLS    8   // 0=disabled 1=left/right simultaneous update
    00051 #define AIC_VLIR_RIM    7   // Mute: 0=Normal 1=Muted
    00052 #define AIC_VLIR_RIV4   4
    00053 #define AIC_VLIR_RIV3   3
    00054 #define AIC_VLIR_RIV2   2
    00055 #define AIC_VLIR_RIV1   1
    00056 #define AIC_VLIR_RIV0   0
    00057
    00058 // AIC_REG_VOL_HP_LEFT bits
    00059 #define AIC_VHPL_LRS    8   // 0=disabled 1=left/right simultaneous update
    00060 #define AIC_VHPL_LZC    7
    00061
    00062 // AIC_REG_VOL_HP_RIGHT bits
    00063 #define AIC_VHPR_RLS    8   // 0=disabled 1=left/right simultaneous update
    00064 #define AIC_VHPR_RZC    7
    00065
    00066 // AIC_REG_ANALOG_PATH bits
    00067 #define AIC_AP_STA2     8   // sidetone attenuation
    00068 #define AIC_AP_STA1     7
    00069 #define AIC_AP_STA0     6
    00070 #define AIC_AP_STE      5   // sidetone enable
    00071 #define AIC_AP_DAC      4   // DAC enable: 0=off 1=on
    00072 #define AIC_AP_BYP      3   // analog bypass linein->lineout: 0=disabled
    00073 #define AIC_AP_INSEL    2   // ADC input select: 0=line 1=mic
    00074 #define AIC_AP_MICM     1   // MIC mute:  0=normal 1=mute
    00075 #define AIC_AP_MICB     0   // MIC boost: 0=0dB    1=+20dB
    00076
    00077 // AIC_REG_DIGITAL_PATH bits
    00078 #define AIC_DP_DACM     3   // DAC mute: 0=disabled
    00079 #define AIC_DP_DEEMP1   2   // De-emphasis: 00=off 01=32KHz 10=44.1KHz 11=48KHz
    00080 #define AIC_DP_DEEMP0   1
    00081 #define AIC_DP_ADCHP    0   // ADC high-pass: 0=disabled
    00082
    00083 // AIC_REG_POWERDOWN bits
    00084 #define AIC_PD_OFF      7   // 0=power on 1=power off
    00085 #define AIC_PD_CLK      6
    00086 #define AIC_PD_OSC      5
    00087 #define AIC_PD_OUT      4
    00088 #define AIC_PD_DAC      3
    00089 #define AIC_PD_ADC      2
    00090 #define AIC_PD_MIC      1
    00091 #define AIC_PD_LINE     0
    00092
    00093 // AIC_REG_INTERFACE_FORMAT bits
    00094 #define AIC_IF_MS       6   // Master/Slave: 0=slave 1=master
    00095 #define AIC_IF_LRSWAP   5   // DAC LR swap: 0=disabled
    00096 #define AIC_IF_LRP      4   // left/right phase
    00097 #define AIC_IF_IWL1     3   // Input Length:
    00098 #define AIC_IF_IWL0     2   //  00=16bit 01=20bit 10=24bit 11=32bit
    00099 #define AIC_IF_FOR1     1   // Data Format:
    00100 #define AIC_IF_FOR0     0   //  11=DSP 10=I2S MSB 1st left 01=MSB 1st left 00=MSB 1st right
    00101
    00102 #define AIC_IF_16BIT    0x00
    00103 #define AIC_IF_20BIT    0x04
    00104 #define AIC_IF_24BIT    0x08
    00105 #define AIC_IF_32BIT    0x0C
    00106
    00107 #define AIC_IF_DSP      0x03
    00108 #define AIC_IF_I2S      0x02
    00109 #define AIC_IF_MSBL     0x01
    00110 #define AIC_IF_MSBR     0x00
    00111
    00112 // AIC_REG_SAMPLE_RATE bits
    00113 #define AIC_SR_CLKOUT   7   // Clock output divider: 0=MCLK 1=MCLK/2
    00114 #define AIC_SR_CLKIN    6   // Clock input divider:  0=MCLK 1=MCLK/2
    00115 #define AIC_SR_SR3      5   // Sample Rate Control:
    00116 #define AIC_SR_SR2      4
    00117 #define AIC_SR_SR1      3
    00118 #define AIC_SR_SR0      2
    00119 #define AIC_SR_BOSR     1   // Base Oversampl. Rate: Nor:0=256fs 1=384fs USB: 0=250fs 1=272fs
    00120 #define AIC_SR_USB      0   // Clock mode select: 0=Normal 1=USB (12MHz)
    00121
    00122 #define AIC_SR_USB_96KHZ    (BIT(AIC_SR_USB) | BIT(AIC_SR_SR0) | BIT(AIC_SR_SR1) | BIT(AIC_SR_SR2))
    00123 #define AIC_SR_USB_48KHZ    (BIT(AIC_SR_USB))
    00124 #define AIC_SR_USB_44KHZ    (BIT(AIC_SR_USB) | BIT(AIC_SR_BOSR) | BIT(AIC_SR_SR3))
    00125 #define AIC_SR_USB_32KHZ    (BIT(AIC_SR_USB) | BIT(AIC_SR_SR1) | BIT(AIC_SR_SR2))
    00126 #define AIC_SR_USB_8KHZ     (BIT(AIC_SR_USB) | BIT(AIC_SR_SR0) | BIT(AIC_SR_SR1))
    00127
    00128 #define AIC_SR_18432_96KHZ  (BIT(AIC_SR_BOSR) | BIT(AIC_SR_SR0) | BIT(AIC_SR_SR1) | BIT(AIC_SR_SR2))
    00129 #define AIC_SR_18432_48KHZ  (BIT(AIC_SR_BOSR))
    00130 #define AIC_SR_18432_32KHZ  (BIT(AIC_SR_BOSR) | BIT(AIC_SR_SR1) | BIT(AIC_SR_SR2))
    00131 #define AIC_SR_18432_8KHZ   (BIT(AIC_SR_BOSR) | BIT(AIC_SR_SR0) | BIT(AIC_SR_SR1))
    00132
    00133
    00134 // AIC_REG_DIGITAL_IF_ACT bits
    00135
    00136 void aicInit(void);
    00137 int  aicWriteReg(u16 regdata);
    00138
    00139 void aicSetVolumeHp(u08 volume);
    00140 void aicSetVolumeLineIn(u08 volume);
    00141 void aicSetVolumeLineOut(u08 volume);
    00142
    00143 void aicDigitalEnable(void);
    00144
    00145
    00146
    00147 #endif