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# processor.c

    00001 /*! \file processor.c \brief LPC2100 Processor Initialization and Support. */
    00002 //*****************************************************************************
    00003 //
    00004 // File Name    : 'processor.c'
    00005 // Title        : LPC2100 Processor Initialization and Support
    00006 // Author       : Pascal Stang - Copyright (C) 2004
    00007 // Created      : 2004.05.05
    00008 // Revised      : 2004.07.12
    00009 // Version      : 0.1
    00010 // Target MCU   : ARM processors
    00011 // Editor Tabs  : 4
    00012 //
    00013 // NOTE: This code is currently below version 1.0, and therefore is considered
    00014 // to be lacking in some functionality or documentation, or may not be fully
    00015 // tested.  Nonetheless, you can expect most functions to work.
    00016 //
    00017 // This code is distributed under the GNU Public License
    00018 //      which can be found at http://www.gnu.org/licenses/gpl.txt
    00019 //
    00020 //*****************************************************************************
    00021
    00022 #include "lpc2000.h"
    00023
    00024 #include "global.h"
    00025 #include "processor.h"
    00026
    00027 void processorInit(void)
    00028 {
    00029     // setup processor PLL clock
    00030     // set the PLL multiplier and divisor (auto-computed by lpcSCB.h)
    00031     PLLCFG = PLLCFG_MSEL | PLLCFG_PSEL;
    00032
    00033     // PLL procedure as per LPC2000 datasheet
    00034     PLLCON = PLLCON_PLLE;               // enable PLL
    00035     PLLFEED = 0xAA; PLLFEED = 0x55;     // load the changes
    00036     while(!(PLLSTAT & PLLSTAT_LOCK));   // wait until PLL locks
    00037     PLLCON = PLLCON_PLLE | PLLCON_PLLC; // now connect PLL as system clock
    00038     PLLFEED = 0xAA; PLLFEED = 0x55;     // load the changes
    00039
    00040     // setup memory access timing (memory accelerator module)
    00041     MAMTIM = MAMTIM_CYCLES;             // set cycle time
    00042     MAMCR = MAMCR_FULL;                 // set full acceleration features
    00043
    00044     // setup peripheral bus speed (set by global.h)
    00045     VPBDIV = VPBDIV_VALUE;
    00046
    00047     // initialize processor and VIC interrupt handling
    00048     processorVicInit();
    00049 }
    00050
    00051 unsigned int processorDisableInt(unsigned int cpsr_mask)
    00052 {
    00053     unsigned int cpsr;
    00054     // read CPSR
    00055     asm volatile ("mrs  %0, cpsr" : "=r" (cpsr) : );
    00056     // set interrupt disable bit and write CPSR
    00057     asm volatile ("msr  cpsr, %0" : : "r" (cpsr|(cpsr_mask&CPSR_MASK_INT)) );
    00058     // return the original CPSR
    00059     return cpsr;
    00060 }
    00061
    00062 unsigned int processorEnableInt(unsigned int cpsr_mask)
    00063 {
    00064     unsigned int cpsr;
    00065     // read CPSR
    00066     asm volatile ("mrs  %0, cpsr" : "=r" (cpsr) : );
    00067     // clear interrupt disable bit(s) and write CPSR
    00068     asm volatile ("msr  cpsr, %0" : : "r" (cpsr&~(cpsr_mask&CPSR_MASK_INT)) );
    00069     // return the original CPSR
    00070     return cpsr;
    00071 }
    00072
    00073 unsigned int processorRestoreInt(unsigned int cpsr_orig)
    00074 {
    00075     unsigned int cpsr;
    00076     // read CPSR
    00077     asm volatile ("mrs  %0, cpsr" : "=r" (cpsr) : );
    00078     // clear interrupt disable bit(s) and write CPSR
    00079     asm volatile ("msr  cpsr, %0" : : "r" ( (cpsr&~CPSR_MASK_INT) | (cpsr_orig&CPSR_MASK_INT)) );
    00080     // return the original CPSR
    00081     return cpsr;
    00082 }
    00083
    00084 void processorVicInit(void)
    00085 {
    00086     int i;
    00087
    00088     // first disable all interrupts at the VIC
    00089     VICIntEnClear = 0xFFFF;
    00090     // clear soft interrupts
    00091     VICSoftIntClear = 0xFFFF;
    00092     // reset all interrupts as IRQ (not FIQ)
    00093     VICIntSelect = 0;
    00094
    00095     // TODO: make and register a spurious/default intr handler
    00096
    00097     // reset all vectors in the VIC
    00098     for(i=0; i<16; i++)
    00099     {
    00100         (&VICVectCntl0)[i] = 0;
    00101         (&VICVectAddr0)[i] = 0;
    00102     }
    00103     // set default handler
    00104     VICDefVectAddr = 0;
    00105 }
    00106
    00107 void processorVicAttach(int pid, int srcmode, void (*userFunc)(void) )
    00108 {
    00109     // first disable the interrupt at the AIC
    00110     VICIntEnClear = (1<<pid);
    00111     // assign a VIC slot
    00112     (&VICVectCntl0)[pid] = VIC_ENABLE | pid;
    00113     // set a new interrupt handler routine pointer
    00114     (&VICVectAddr0)[pid] = (unsigned int)userFunc;
    00115     // set interrupt as IRQ
    00116     VICIntSelect &= ~(1<<pid);
    00117     // enable the interrupt at the VIC
    00118     VICIntEnable |= (1<<pid);
    00119 }
    00120
    00121 void processorVicDetach(int pid)
    00122 {
    00123     // first disable the interrupt at the VIC
    00124     VICIntEnClear = (1<<pid);
    00125     // clear the interrupt flag in the VIC
    00126     // = (1<<pid);
    00127     // clear the interrupt handler routine pointer
    00128     (&VICVectAddr0)[pid] = 0;
    00129 }