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# enc28j60.h

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    00001 /*! \file enc28j60.h \brief Microchip ENC28J60 Ethernet Interface Driver. */
    00002 //*****************************************************************************
    00003 //
    00004 // File Name    : 'enc28j60.h'
    00005 // Title        : Microchip ENC28J60 Ethernet Interface Driver
    00006 // Author       : Pascal Stang (c)2005
    00007 // Created      : 9/22/2005
    00008 // Revised      : 9/22/2005
    00009 // Version      : 0.1
    00010 // Target MCU   : Atmel AVR series
    00011 // Editor Tabs  : 4
    00012 //
    00013 /// \ingroup network
    00014 /// \defgroup enc28j60 Microchip ENC28J60 Ethernet Interface Driver (enc28j60.c)
    00015 /// \code #include "net/enc28j60.h" \endcode
    00016 /// \par Overview
    00017 ///     This driver provides initialization and transmit/receive
    00018 /// functions for the Microchip ENC28J60 10Mb Ethernet Controller and PHY.
    00019 /// This chip is novel in that it is a full MAC+PHY interface all in a 28-pin
    00020 /// chip, using an SPI interface to the host processor.
    00021 ///
    00022 //
    00023 //*****************************************************************************
    00024 //@{
    00025
    00026 #ifndef ENC28J60_H
    00027 #define ENC28J60_H
    00028
    00029 #include "global.h"
    00030
    00031 #define nop()   asm volatile ("nop")
    00032
    00033 // ENC28J60 Control Registers
    00034 // Control register definitions are a combination of address,
    00035 // bank number, and Ethernet/MAC/PHY indicator bits.
    00036 // - Register address   (bits 0-4)
    00037 // - Bank number        (bits 5-6)
    00038 // - MAC/PHY indicator  (bit 7)
    00039 #define ADDR_MASK   0x1F
    00040 #define BANK_MASK   0x60
    00041 #define SPRD_MASK   0x80
    00042 // All-bank registers
    00043 #define EIE         0x1B
    00044 #define EIR         0x1C
    00045 #define ESTAT       0x1D
    00046 #define ECON2       0x1E
    00047 #define ECON1       0x1F
    00048 // Bank 0 registers
    00049 #define ERDPTL      (0x00|0x00)
    00050 #define ERDPTH      (0x01|0x00)
    00051 #define EWRPTL      (0x02|0x00)
    00052 #define EWRPTH      (0x03|0x00)
    00053 #define ETXSTL      (0x04|0x00)
    00054 #define ETXSTH      (0x05|0x00)
    00055 #define ETXNDL      (0x06|0x00)
    00056 #define ETXNDH      (0x07|0x00)
    00057 #define ERXSTL      (0x08|0x00)
    00058 #define ERXSTH      (0x09|0x00)
    00059 #define ERXNDL      (0x0A|0x00)
    00060 #define ERXNDH      (0x0B|0x00)
    00061 #define ERXRDPTL    (0x0C|0x00)
    00062 #define ERXRDPTH    (0x0D|0x00)
    00063 #define ERXWRPTL    (0x0E|0x00)
    00064 #define ERXWRPTH    (0x0F|0x00)
    00065 #define EDMASTL     (0x10|0x00)
    00066 #define EDMASTH     (0x11|0x00)
    00067 #define EDMANDL     (0x12|0x00)
    00068 #define EDMANDH     (0x13|0x00)
    00069 #define EDMADSTL    (0x14|0x00)
    00070 #define EDMADSTH    (0x15|0x00)
    00071 #define EDMACSL     (0x16|0x00)
    00072 #define EDMACSH     (0x17|0x00)
    00073 // Bank 1 registers
    00074 #define EHT0        (0x00|0x20)
    00075 #define EHT1        (0x01|0x20)
    00076 #define EHT2        (0x02|0x20)
    00077 #define EHT3        (0x03|0x20)
    00078 #define EHT4        (0x04|0x20)
    00079 #define EHT5        (0x05|0x20)
    00080 #define EHT6        (0x06|0x20)
    00081 #define EHT7        (0x07|0x20)
    00082 #define EPMM0       (0x08|0x20)
    00083 #define EPMM1       (0x09|0x20)
    00084 #define EPMM2       (0x0A|0x20)
    00085 #define EPMM3       (0x0B|0x20)
    00086 #define EPMM4       (0x0C|0x20)
    00087 #define EPMM5       (0x0D|0x20)
    00088 #define EPMM6       (0x0E|0x20)
    00089 #define EPMM7       (0x0F|0x20)
    00090 #define EPMCSL      (0x10|0x20)
    00091 #define EPMCSH      (0x11|0x20)
    00092 #define EPMOL       (0x14|0x20)
    00093 #define EPMOH       (0x15|0x20)
    00094 #define EWOLIE      (0x16|0x20)
    00095 #define EWOLIR      (0x17|0x20)
    00096 #define ERXFCON     (0x18|0x20)
    00097 #define EPKTCNT     (0x19|0x20)
    00098 // Bank 2 registers
    00099 #define MACON1      (0x00|0x40|0x80)
    00100 #define MACON2      (0x01|0x40|0x80)
    00101 #define MACON3      (0x02|0x40|0x80)
    00102 #define MACON4      (0x03|0x40|0x80)
    00103 #define MABBIPG     (0x04|0x40|0x80)
    00104 #define MAIPGL      (0x06|0x40|0x80)
    00105 #define MAIPGH      (0x07|0x40|0x80)
    00106 #define MACLCON1    (0x08|0x40|0x80)
    00107 #define MACLCON2    (0x09|0x40|0x80)
    00108 #define MAMXFLL     (0x0A|0x40|0x80)
    00109 #define MAMXFLH     (0x0B|0x40|0x80)
    00110 #define MAPHSUP     (0x0D|0x40|0x80)
    00111 #define MICON       (0x11|0x40|0x80)
    00112 #define MICMD       (0x12|0x40|0x80)
    00113 #define MIREGADR    (0x14|0x40|0x80)
    00114 #define MIWRL       (0x16|0x40|0x80)
    00115 #define MIWRH       (0x17|0x40|0x80)
    00116 #define MIRDL       (0x18|0x40|0x80)
    00117 #define MIRDH       (0x19|0x40|0x80)
    00118 // Bank 3 registers
    00119 #define MAADR1      (0x00|0x60|0x80)
    00120 #define MAADR0      (0x01|0x60|0x80)
    00121 #define MAADR3      (0x02|0x60|0x80)
    00122 #define MAADR2      (0x03|0x60|0x80)
    00123 #define MAADR5      (0x04|0x60|0x80)
    00124 #define MAADR4      (0x05|0x60|0x80)
    00125 #define EBSTSD      (0x06|0x60)
    00126 #define EBSTCON     (0x07|0x60)
    00127 #define EBSTCSL     (0x08|0x60)
    00128 #define EBSTCSH     (0x09|0x60)
    00129 #define MISTAT      (0x0A|0x60|0x80)
    00130 #define EREVID      (0x12|0x60)
    00131 #define ECOCON      (0x15|0x60)
    00132 #define EFLOCON     (0x17|0x60)
    00133 #define EPAUSL      (0x18|0x60)
    00134 #define EPAUSH      (0x19|0x60)
    00135 // PHY registers
    00136 #define PHCON1      0x00
    00137 #define PHSTAT1     0x01
    00138 #define PHHID1      0x02
    00139 #define PHHID2      0x03
    00140 #define PHCON2      0x10
    00141 #define PHSTAT2     0x11
    00142 #define PHIE        0x12
    00143 #define PHIR        0x13
    00144 #define PHLCON      0x14
    00145
    00146 // ENC28J60 EIE Register Bit Definitions
    00147 #define EIE_INTIE       0x80
    00148 #define EIE_PKTIE       0x40
    00149 #define EIE_DMAIE       0x20
    00150 #define EIE_LINKIE      0x10
    00151 #define EIE_TXIE        0x08
    00152 #define EIE_WOLIE       0x04
    00153 #define EIE_TXERIE      0x02
    00154 #define EIE_RXERIE      0x01
    00155 // ENC28J60 EIR Register Bit Definitions
    00156 #define EIR_PKTIF       0x40
    00157 #define EIR_DMAIF       0x20
    00158 #define EIR_LINKIF      0x10
    00159 #define EIR_TXIF        0x08
    00160 #define EIR_WOLIF       0x04
    00161 #define EIR_TXERIF      0x02
    00162 #define EIR_RXERIF      0x01
    00163 // ENC28J60 ESTAT Register Bit Definitions
    00164 #define ESTAT_INT       0x80
    00165 #define ESTAT_LATECOL   0x10
    00166 #define ESTAT_RXBUSY    0x04
    00167 #define ESTAT_TXABRT    0x02
    00168 #define ESTAT_CLKRDY    0x01
    00169 // ENC28J60 ECON2 Register Bit Definitions
    00170 #define ECON2_AUTOINC   0x80
    00171 #define ECON2_PKTDEC    0x40
    00172 #define ECON2_PWRSV     0x20
    00173 #define ECON2_VRPS      0x08
    00174 // ENC28J60 ECON1 Register Bit Definitions
    00175 #define ECON1_TXRST     0x80
    00176 #define ECON1_RXRST     0x40
    00177 #define ECON1_DMAST     0x20
    00178 #define ECON1_CSUMEN    0x10
    00179 #define ECON1_TXRTS     0x08
    00180 #define ECON1_RXEN      0x04
    00181 #define ECON1_BSEL1     0x02
    00182 #define ECON1_BSEL0     0x01
    00183 // ENC28J60 MACON1 Register Bit Definitions
    00184 #define MACON1_LOOPBK   0x10
    00185 #define MACON1_TXPAUS   0x08
    00186 #define MACON1_RXPAUS   0x04
    00187 #define MACON1_PASSALL  0x02
    00188 #define MACON1_MARXEN   0x01
    00189 // ENC28J60 MACON2 Register Bit Definitions
    00190 #define MACON2_MARST    0x80
    00191 #define MACON2_RNDRST   0x40
    00192 #define MACON2_MARXRST  0x08
    00193 #define MACON2_RFUNRST  0x04
    00194 #define MACON2_MATXRST  0x02
    00195 #define MACON2_TFUNRST  0x01
    00196 // ENC28J60 MACON3 Register Bit Definitions
    00197 #define MACON3_PADCFG2  0x80
    00198 #define MACON3_PADCFG1  0x40
    00199 #define MACON3_PADCFG0  0x20
    00200 #define MACON3_TXCRCEN  0x10
    00201 #define MACON3_PHDRLEN  0x08
    00202 #define MACON3_HFRMLEN  0x04
    00203 #define MACON3_FRMLNEN  0x02
    00204 #define MACON3_FULDPX   0x01
    00205 // ENC28J60 MICMD Register Bit Definitions
    00206 #define MICMD_MIISCAN   0x02
    00207 #define MICMD_MIIRD     0x01
    00208 // ENC28J60 MISTAT Register Bit Definitions
    00209 #define MISTAT_NVALID   0x04
    00210 #define MISTAT_SCAN     0x02
    00211 #define MISTAT_BUSY     0x01
    00212 // ENC28J60 PHY PHCON1 Register Bit Definitions
    00213 #define PHCON1_PRST     0x8000
    00214 #define PHCON1_PLOOPBK  0x4000
    00215 #define PHCON1_PPWRSV   0x0800
    00216 #define PHCON1_PDPXMD   0x0100
    00217 // ENC28J60 PHY PHSTAT1 Register Bit Definitions
    00218 #define PHSTAT1_PFDPX   0x1000
    00219 #define PHSTAT1_PHDPX   0x0800
    00220 #define PHSTAT1_LLSTAT  0x0004
    00221 #define PHSTAT1_JBSTAT  0x0002
    00222 // ENC28J60 PHY PHCON2 Register Bit Definitions
    00223 #define PHCON2_FRCLINK  0x4000
    00224 #define PHCON2_TXDIS    0x2000
    00225 #define PHCON2_JABBER   0x0400
    00226 #define PHCON2_HDLDIS   0x0100
    00227
    00228 // ENC28J60 Packet Control Byte Bit Definitions
    00229 #define PKTCTRL_PHUGEEN     0x08
    00230 #define PKTCTRL_PPADEN      0x04
    00231 #define PKTCTRL_PCRCEN      0x02
    00232 #define PKTCTRL_POVERRIDE   0x01
    00233
    00234 // SPI operation codes
    00235 #define ENC28J60_READ_CTRL_REG  0x00
    00236 #define ENC28J60_READ_BUF_MEM   0x3A
    00237 #define ENC28J60_WRITE_CTRL_REG 0x40
    00238 #define ENC28J60_WRITE_BUF_MEM  0x7A
    00239 #define ENC28J60_BIT_FIELD_SET  0x80
    00240 #define ENC28J60_BIT_FIELD_CLR  0xA0
    00241 #define ENC28J60_SOFT_RESET     0xFF
    00242
    00243
    00244 // buffer boundaries applied to internal 8K ram
    00245 //  entire available packet buffer space is allocated
    00246 #define TXSTART_INIT    0x0000  // start TX buffer at 0
    00247 #define RXSTART_INIT    0x0600  // give TX buffer space for one full ethernet frame (~1500 bytes)
    00248 #define RXSTOP_INIT     0x1FFF  // receive buffer gets the rest
    00249
    00250 #define MAX_FRAMELEN    1518    // maximum ethernet frame length
    00251
    00252 // Ethernet constants
    00253 #define ETHERNET_MIN_PACKET_LENGTH  0x3C
    00254 //#define ETHERNET_HEADER_LENGTH        0x0E
    00255
    00256 #define ENC28J60_CONTROL_PORT   PORTB
    00257 #define ENC28J60_CONTROL_DDR    DDRB
    00258 #define ENC28J60_CONTROL_CS     0
    00259
    00260 // MAC address for this interface
    00261 #ifdef ETHADDR0
    00262 #define ENC28J60_MAC0 ETHADDR0
    00263 #define ENC28J60_MAC1 ETHADDR1
    00264 #define ENC28J60_MAC2 ETHADDR2
    00265 #define ENC28J60_MAC3 ETHADDR3
    00266 #define ENC28J60_MAC4 ETHADDR4
    00267 #define ENC28J60_MAC5 ETHADDR5
    00268 #else
    00269 #define ENC28J60_MAC0 '0'
    00270 #define ENC28J60_MAC1 'F'
    00271 #define ENC28J60_MAC2 'F'
    00272 #define ENC28J60_MAC3 'I'
    00273 #define ENC28J60_MAC4 'C'
    00274 #define ENC28J60_MAC5 'E'
    00275 #endif
    00276
    00277
    00278 // functions
    00279 #include "nic.h"
    00280
    00281 // setup ports for I/O
    00282 //void ax88796SetupPorts(void);
    00283
    00284 //! do a ENC28J60 read operation
    00285 u08 enc28j60ReadOp(u08 op, u08 address);
    00286 //! do a ENC28J60 write operation
    00287 void enc28j60WriteOp(u08 op, u08 address, u08 data);
    00288 //! read the packet buffer memory
    00289 void enc28j60ReadBuffer(u16 len, u08* data);
    00290 //! write the packet buffer memory
    00291 void enc28j60WriteBuffer(u16 len, u08* data);
    00292 //! set the register bank for register at address
    00293 void enc28j60SetBank(u08 address);
    00294 //! read ax88796 register
    00295 u08 enc28j60Read(u08 address);
    00296 //! write ax88796 register
    00297 void enc28j60Write(u08 address, u08 data);
    00298 //! read a PHY register
    00299 u16 enc28j60PhyRead(u08 address);
    00300 //! write a PHY register
    00301 void enc28j60PhyWrite(u08 address, u16 data);
    00302
    00303 //! initialize the ethernet interface for transmit/receive
    00304 void enc28j60Init(void);
    00305
    00306 //! Packet transmit function.
    00307 /// Sends a packet on the network.  It is assumed that the packet is headed by a valid ethernet header.
    00308 /// \param len      Length of packet in bytes.
    00309 /// \param packet   Pointer to packet data.
    00310 void enc28j60PacketSend(unsigned int len, unsigned char* packet);
    00311
    00312 //! Packet receive function.
    00313 /// Gets a packet from the network receive buffer, if one is available.
    00314 /// The packet will by headed by an ethernet header.
    00315 /// \param  maxlen  The maximum acceptable length of a retrieved packet.
    00316 /// \param  packet  Pointer where packet data should be stored.
    00317 /// \return Packet length in bytes if a packet was retrieved, zero otherwise.
    00318 unsigned int enc28j60PacketReceive(unsigned int maxlen, unsigned char* packet);
    00319
    00320 //! execute procedure for recovering from a receive overflow
    00321 /// this should be done when the receive memory fills up with packets
    00322 void enc28j60ReceiveOverflowRecover(void);
    00323
    00324 //! formatted print of important ENC28J60 registers
    00325 void enc28j60RegDump(void);
    00326
    00327 #endif
    00328 //@}