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# processor.c

    00001 /*! \file processor.c \brief ADuC7000 Processor Initialization and Support. */
    00002 //*****************************************************************************
    00003 //
    00004 // File Name    : 'processor.c'
    00005 // Title        : ADuC7000 Processor Initialization and Support
    00006 // Author       : Pascal Stang - Copyright (C) 2006
    00007 // Created      : 2006.01.30
    00008 // Revised      : 2006.02.20
    00009 // Version      : 0.1
    00010 // Target MCU   : ARM processors
    00011 // Editor Tabs  : 4
    00012 //
    00013 // NOTE: This code is currently below version 1.0, and therefore is considered
    00014 // to be lacking in some functionality or documentation, or may not be fully
    00015 // tested.  Nonetheless, you can expect most functions to work.
    00016 //
    00017 //*****************************************************************************
    00018
    00019 // Include the processor definitions
    00020 #include "aduc7026.h"
    00021 // Include project-level definitions
    00022 #include "global.h"
    00023
    00024 #include "processor.h"
    00025
    00026 // Low-level processor initialization and clock control
    00027 void processorInit( void)
    00028 {
    00029     // setup PLL
    00030     PLLKEY1 = 0xAA;
    00031     PLLCON =  0x01;
    00032     PLLKEY2 = 0x55;
    00033
    00034     POWKEY1 = 0x01;
    00035     POWCON =  0x00;
    00036     POWKEY2 = 0xF4;
    00037 }
    00038
    00039 unsigned int processorDisableInt(unsigned int cpsr_mask)
    00040 {
    00041     unsigned int cpsr;
    00042     // read CPSR
    00043     asm volatile ("mrs  %0, cpsr" : "=r" (cpsr) : );
    00044     // set interrupt disable bit and write CPSR
    00045     asm volatile ("msr  cpsr, %0" : : "r" (cpsr|(cpsr_mask&CPSR_MASK_INT)) );
    00046     // return the original CPSR
    00047     return cpsr;
    00048 }
    00049
    00050 unsigned int processorEnableInt(unsigned int cpsr_mask)
    00051 {
    00052     unsigned int cpsr;
    00053     // read CPSR
    00054     asm volatile ("mrs  %0, cpsr" : "=r" (cpsr) : );
    00055     // clear interrupt disable bit(s) and write CPSR
    00056     asm volatile ("msr  cpsr, %0" : : "r" (cpsr&~(cpsr_mask&CPSR_MASK_INT)) );
    00057     // return the original CPSR
    00058     return cpsr;
    00059 }
    00060
    00061 unsigned int processorRestoreInt(unsigned int cpsr_orig)
    00062 {
    00063     unsigned int cpsr;
    00064     // read CPSR
    00065     asm volatile ("mrs  %0, cpsr" : "=r" (cpsr) : );
    00066     // clear interrupt disable bit(s) and write CPSR
    00067     asm volatile ("msr  cpsr, %0" : : "r" ( (cpsr&~&CPSR_MASK_INT) | (cpsr_orig&CPSR_MASK_INT)) );
    00068     // return the original CPSR
    00069     return cpsr;
    00070 }