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# processor.h

    00001 /*! \file processor.h \brief AT91SAM7S Processor Initialization and Support. */
    00002 //*****************************************************************************
    00003 //
    00004 // File Name    : 'processor.h'
    00005 // Title        : AT91SAM7S Processor Initialization and Support
    00006 // Author       : Pascal Stang - Copyright (C) 2006
    00007 // Created      : 2006.01.30
    00008 // Revised      : 2006.02.20
    00009 // Version      : 0.1
    00010 // Target MCU   : ARM processors
    00011 // Editor Tabs  : 4
    00012 //
    00013 // NOTE: This code is currently below version 1.0, and therefore is considered
    00014 // to be lacking in some functionality or documentation, or may not be fully
    00015 // tested.  Nonetheless, you can expect most functions to work.
    00016 //
    00017 /// \ingroup driver_arm_at91
    00018 /// \defgroup processor_at91 AT91SAM7S Processor Initialization and Support (armlib/arch/at91/processor.c)
    00019 /// \code #include "processor.h" \endcode
    00020 /// \par Overview
    00021 ///     To be written...
    00022 //
    00023 //*****************************************************************************
    00024 //@{
    00025
    00026 #ifndef ARMLIB_PROCESSOR_H
    00027 #define ARMLIB_PROCESSOR_H
    00028
    00029 // masks for use with enable/disable ARM core interrupts
    00030 #define CPSR_MASK_IRQ 0x00000080
    00031 #define CPSR_MASK_FIQ 0x00000040
    00032 #define CPSR_MASK_INT (CPSR_MASK_IRQ | CPSR_MASK_FIQ)
    00033
    00034 // general processor functions
    00035 void processorInit(void);
    00036 unsigned int processorEnableInt(unsigned int cpsr_mask);
    00037 unsigned int processorDisableInt(unsigned int cpsr_mask);
    00038 unsigned int processorRestoreInt(unsigned int cpsr_orig);
    00039
    00040 // use at beginning of any critical code block to disable interrupts (prevents interruptions)
    00041 #define CRITICAL_SECTION_BEGIN      unsigned int _cpsr = processorDisableInt(CPSR_MASK_INT)
    00042 // use at end of any critical code block to restore interrupts
    00043 #define CRITICAL_SECTION_END        processorRestoreInt(_cpsr)
    00044
    00045 // SYSPID defines for use with processorAicAttachSys()
    00046 #define SYSPID_PITC 0   // periodic interval timer
    00047 #define SYSPID_DBGU 1   // debug uart
    00048 #define SYSPID_RTTC 2   // real-time timer
    00049 #define SYSPID_EFC  3   // embedded flash controller
    00050 #define SYSPID_PMC  4   // power management controller
    00051 #define SYSPID_NUM  5   // total number of system interrupt peripherals
    00052
    00053 // AIC functions
    00054
    00055 // initialize the AIC vectors
    00056 void processorAicInit(void);
    00057
    00058 // Attach an interrupt handler on specified peripheral-ID interrupt channel.
    00059 //  Also enables interrupt in AIC.
    00060 void processorAicAttach(int pid, int srcmode, void (*userFunc)(void) );
    00061
    00062 // Detach current interrupt handler on specified peripheral-ID interrupt channel.
    00063 //  Also disables interrupt in AIC.
    00064 void processorAicDetach(int pid);
    00065
    00066 // Attach an interrupt handler on specified sub-peripheral of system interrupt channel (int ch 2).
    00067 void processorAicAttachSys(int syspid, void (*userFunc)(void) );
    00068
    00069 // Interrupt handler for system interrupt (internal).
    00070 // function determines source of interrupt and calls appropriate attached function
    00071 void processorSysIntService(void);
    00072
    00073
    00074 // Macro for use upon entry to naked interrupt handler
    00075 // - saves non-banked CPU registers and SPSR onto IRQ/FIQ stack
    00076 #define ISR_ENTRY() asm volatile(" sub   lr, lr,#4\n" \
    00077                                  " stmfd sp!,{r0-r12,lr}\n" \
    00078                                  " mrs   r1, spsr\n" \
    00079                                  " stmfd sp!,{r1}")
    00080
    00081 // Macro for use upon exit from naked interrupt handler
    00082 // - restores SPSR and non-banked CPU registers from IRQ/FIQ stack
    00083 #define ISR_EXIT()  asm volatile(" ldmfd sp!,{r1}\n" \
    00084                                  " msr   spsr_c,r1\n" \
    00085                                  " ldmfd sp!,{r0-r12,pc}^")
    00086
    00087 #endif
    00088 //@}