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# membus_slow.c

    00001 /*! \file membus.c \brief Software-driven Memory Bus for ARMmini-LPC210x. */
    00002 //*****************************************************************************
    00003 //
    00004 // File Name    : 'membus.c'
    00005 // Title        : Software-driven Memory Bus for ARMmini-LPC210x
    00006 // Author       : Pascal Stang - Copyright (C) 2004
    00007 // Created      : 2004.05.05
    00008 // Revised      : 2004.07.12
    00009 // Version      : 0.1
    00010 // Target MCU   : ARM processors
    00011 // Editor Tabs  : 4
    00012 //
    00013 // NOTE: This code is currently below version 1.0, and therefore is considered
    00014 // to be lacking in some functionality or documentation, or may not be fully
    00015 // tested.  Nonetheless, you can expect most functions to work.
    00016 //
    00017 // This code is distributed under the GNU Public License
    00018 //      which can be found at http://www.gnu.org/licenses/gpl.txt
    00019 //
    00020 //*****************************************************************************
    00021
    00022 #include "lpc2000.h"
    00023 #include "global.h"
    00024 #include "processor.h"
    00025 #include "timer.h"
    00026 #include "membus.h"
    00027
    00028 void membusInit(void)
    00029 {
    00030     // setup I/O lines
    00031     IOCLR = MEMBUS_LATCH;
    00032     IOSET = MEMBUS_nRD;
    00033     IOSET = MEMBUS_nWR;
    00034     // set inputs
    00035     IODIR &= ~P015;
    00036     // set outputs
    00037     IODIR |= (MEMBUS_IO | MEMBUS_LATCH | MEMBUS_nRD | MEMBUS_nWR);
    00038 }
    00039
    00040 uint16_t membusRead(uint16_t addr)
    00041 {
    00042     uint16_t data;
    00043     int flags;
    00044
    00045     // disable interrupts
    00046     flags = disableIRQ();
    00047     // switch bus to output
    00048     IODIR |= MEMBUS_IO;
    00049     // assert address
    00050     IOCLR = MEMBUS_IO;
    00051     IOSET = addr<<16;
    00052     // latch address
    00053     IOSET = MEMBUS_LATCH;
    00054     // delay
    00055     MEMBUS_DELAY;
    00056     IOCLR = MEMBUS_LATCH | MEMBUS_IO;
    00057
    00058     // switch bus to input
    00059     IODIR &= ~MEMBUS_IO;
    00060     // assert read
    00061     IOCLR = MEMBUS_nRD;
    00062     // delay
    00063     MEMBUS_DELAY;
    00064     // read in data
    00065     data = IOPIN>>16;
    00066     // release read
    00067     IOSET = MEMBUS_nRD;
    00068     // restore interrupts
    00069     restoreIRQ(flags);
    00070
    00071     return data;
    00072 }
    00073
    00074 void membusWrite(uint16_t addr, uint16_t data)
    00075 {
    00076     int flags;
    00077
    00078     // disable interrupts
    00079     flags = disableIRQ();
    00080     // switch bus to output
    00081     IODIR |= MEMBUS_IO;
    00082     // assert address
    00083     IOCLR = MEMBUS_IO;
    00084     IOSET = addr<<16;
    00085     // latch address
    00086     IOSET = MEMBUS_LATCH;
    00087     // delay
    00088     MEMBUS_DELAY;
    00089     IOCLR = MEMBUS_LATCH | MEMBUS_IO;
    00090
    00091     // output data
    00092     IOCLR = MEMBUS_IO;
    00093     IOSET = ((uint32_t)data)<<16;
    00094     // assert write
    00095     IOCLR = MEMBUS_nWR;
    00096     // delay
    00097     MEMBUS_DELAY;
    00098     // release write
    00099     IOSET = MEMBUS_nWR;
    00100     // restore interrupts
    00101     restoreIRQ(flags);
    00102 }