Main Page | Modules | Data Structures | Directories | File List | Data Fields | Globals | Related Pages

# ax88796.h

Go to the documentation of this file.

    00001 /*! \file ax88796.h \brief ASIX AX88796 Ethernet Interface Driver. */
    00002 //*****************************************************************************
    00003 //
    00004 // File Name    : 'ax88796.h'
    00005 // Title        : ASIX AX88796 Ethernet Interface Driver
    00006 // Author       : Pascal Stang
    00007 // Created      : 10/22/2002
    00008 // Revised      : 8/22/2005
    00009 // Version      : 0.1
    00010 // Target MCU   : Atmel AVR series
    00011 // Editor Tabs  : 4
    00012 //
    00013 /// \ingroup network
    00014 /// \defgroup ax88796 ASIX AX88796 Ethernet Interface Driver (ax88796.c)
    00015 /// \code #include "net/ax88796.h" \endcode
    00016 /// \par Overview
    00017 ///     This driver provides initialization and transmit/receive
    00018 /// functions for the ASIX AX88796 10/100Mb Ethernet Controller and PHY.
    00019 ///
    00020 /// Based in part on code by Louis Beaudoin (www.embedded-creations.com).
    00021 /// Thanks to Adam Dunkels and Louis Beaudoin for providing the initial
    00022 /// structure in which to write this driver.
    00023 //
    00024 //*****************************************************************************
    00025 //@{
    00026
    00027 #ifndef AX88796_H
    00028 #define AX88796_H
    00029
    00030 #include "global.h"
    00031
    00032 #define nop()   asm volatile ("nop")
    00033
    00034 // AX88796/NE2000 Control Register Offsets
    00035 // Page 0 - Read/Write
    00036 #define CR          0x00    // Command Register
    00037 #define PSTART      0x01    // Page Start Register
    00038 #define PSTOP       0x02    // Page Stop Register
    00039 #define BNRY        0x03    // Boundary Pointer
    00040 #define RDMAPORT    0x10    // DMA Data Port
    00041 #define MEMR        0x14    // MII/EEPROM Access Register
    00042 #define TR          0x15    // Test Register
    00043 #define SPP_DPR     0x18    // Standard Printer Port Data
    00044 #define SSP_SPR     0x19    // Standard Printer Port Status
    00045 #define SSP_CPR     0x1A    // Standard Printer Port Control
    00046 // Page 0 - Read
    00047 #define TSR         0x04    // Transmit Status Register
    00048 #define NCR         0x05    // Number of Collisions Register
    00049 #define ISR         0x07    // Interrupt Status Register
    00050 #define CRDA0       0x08    // Current Remote DMA Address 0
    00051 #define CRDA1       0x09    // Current Remote DMA Address 1
    00052 #define RSR         0x0C    // Receive Status Register
    00053 #define CNTR0       0x0D
    00054 #define CNTR1       0x0E
    00055 #define CNTR2       0x0F
    00056 #define GPI         0x17    // General-Purpose Input
    00057 #define RSTPORT     0x1F    // Reset
    00058 // Page 0 - Write
    00059 #define TPSR        0x04    // Transmit Page Start Address
    00060 #define TBCR0       0x05    // Transmit Byte Count Register 0
    00061 #define TBCR1       0x06    // Transmit Byte Count Register 1
    00062 #define RSAR0       0x08    // Remote Start Address Register 0
    00063 #define RSAR1       0x09    // Remote Start Address Register 1
    00064 #define RBCR0       0x0A    // Remote Byte Count 0
    00065 #define RBCR1       0x0B    // Remote Byte Count 1
    00066 #define RCR         0x0C    // Receive Config Register
    00067 #define TCR         0x0D    // Transmit Config Register
    00068 #define DCR         0x0E    // Data Config Register
    00069 #define IMR         0x0F    // Interrupt Mask Register
    00070 #define GPOC        0x17    // General-Purpose Output Control
    00071 // Page 1 - Read/Write
    00072 #define PAR0        0x01    // Physical Address Register 0
    00073 #define PAR1        0x02    // Physical Address Register 1
    00074 #define PAR2        0x03    // Physical Address Register 2
    00075 #define PAR3        0x04    // Physical Address Register 3
    00076 #define PAR4        0x05    // Physical Address Register 4
    00077 #define PAR5        0x06    // Physical Address Register 5
    00078 #define CURR        0x07    // Page 1
    00079 #define CPR         0x07    // Current Page Register
    00080
    00081 // AX88796 CR Register Bit Definitions
    00082 #define  PS1        0x80
    00083 #define  PS0        0x40
    00084 #define  RD2        0x20
    00085 #define  RD1        0x10
    00086 #define  RD0        0x08
    00087 #define  TXP        0x04
    00088 #define  START      0x02
    00089 #define  STOP       0x01
    00090 // AX88796 RCR Register Bit Definitions
    00091 #define  INTT       0x40
    00092 #define  MON        0x20
    00093 #define  PRO        0x10
    00094 #define  AM         0x08
    00095 #define  AB         0x04
    00096 #define  AR         0x02
    00097 #define  SEP        0x01
    00098 // AX88796 ISR Register Bit Definitions
    00099 #define  RST        0x80
    00100 #define  RDC        0x40
    00101 #define  OVW        0x10
    00102 #define  RXE        0x08
    00103 #define  TXE        0x04
    00104 #define  PTX        0x02
    00105 #define  PRX        0x01
    00106 // AX88796 TEST Register Bit Definitions
    00107 #define  AUTOD      0x01
    00108 #define  RST_B      0x02
    00109 #define  RST_10B    0x04
    00110 #define  RST_TXB    0x08
    00111 // AX88796 GPOC Register Bit Definitions
    00112 #define  GPO0       0x01
    00113 #define  MPSEL      0x10
    00114 #define  MPSET      0x20
    00115 #define  PPDSET     0x40
    00116 // AX88796 MEMR Register Bit Definitions
    00117 #define  MDC        0x01
    00118 #define  MDIR       0x02
    00119 #define  MDI        0x04
    00120 #define  MDO        0x08
    00121 #define  EECS       0x10
    00122 #define  EEI        0x20
    00123 #define  EEO        0x40
    00124 #define  EECLK      0x80
    00125 // AX88796 GPI Register Bit Definitions
    00126 #define  GPI2       0x40
    00127 #define  GPI1       0x20
    00128 #define  GPI0       0x10
    00129 #define  I_SPD      0x04
    00130 #define  I_DPX      0x02
    00131 #define  I_LINK     0x01
    00132 // AX88796 TCR Register Bit Definitions
    00133 #define  FDU        0x80    // full duplex
    00134 #define  PD         0x40    // pad disable
    00135 #define  RLO        0x20    // retry of late collisions
    00136 #define  LB1        0x04    // loopback 1
    00137 #define  LB0        0x02    // loopback 0
    00138 #define  CRC        0x01    // generate CRC
    00139
    00140 // AX88796 Initial Register Values
    00141 // RCR : INT trigger active high and Accept Broadcast ENET packets
    00142 #define RCR_INIT        (INTT | AB)
    00143 #define DCR_INIT        0x00   // was 0x58 for realtek RTL8019
    00144 // TCR : default transmit operation - CRC is generated
    00145 #define TCR_INIT        0x00
    00146 // IMR : interrupt enabled for receive and overrun events
    00147 #define IMR_INIT        0x11    // PRX and OVW interrupt enabled
    00148 // buffer boundaries
    00149 //  transmit has 6 256-byte pages
    00150 //  receive has 26 256-byte pages
    00151 //  entire available packet buffer space is allocated
    00152 #define TXSTART_INIT    0x40
    00153 #define RXSTART_INIT    0x46
    00154 #define RXSTOP_INIT     0x60
    00155
    00156 // Ethernet constants
    00157 #define ETHERNET_MIN_PACKET_LENGTH  0x3C
    00158 //#define ETHERNET_HEADER_LENGTH        0x0E
    00159
    00160 // offsets into ax88796 ethernet packet header
    00161 #define  PKTHEADER_STATUS       0x00    // packet status
    00162 #define  PKTHEADER_NEXTPAGE     0x01    // next buffer page
    00163 #define  PKTHEADER_PKTLENL      0x02    // packet length low
    00164 #define  PKTHEADER_PKTLENH      0x03    // packet length high
    00165
    00166
    00167 // functions
    00168 #include "nic.h"
    00169
    00170 // setup ports for I/O
    00171 void ax88796SetupPorts(void);
    00172
    00173 // read ax88796 register
    00174 #if NIC_CONNECTION == MEMORY_MAPPED
    00175 inline  // declare following function as inline if in MEMORY_MAPPED mode
    00176 #endif
    00177 u08 ax88796Read(u08 address);
    00178
    00179 // write ax88796 register
    00180 #if NIC_CONNECTION == MEMORY_MAPPED
    00181 inline  // declare following function as inline if in MEMORY_MAPPED mode
    00182 #endif
    00183 void ax88796Write(u08 address, u08 data);
    00184
    00185 // initialize the ethernet interface for transmit/receive
    00186 void ax88796Init(void);
    00187
    00188 // packet transmit functions
    00189 void ax88796BeginPacketSend(unsigned int packetLength);
    00190 void ax88796SendPacketData(unsigned char * localBuffer, unsigned int length);
    00191 void ax88796EndPacketSend(void);
    00192
    00193 // packet receive functions
    00194 unsigned int ax88796BeginPacketRetreive(void);
    00195 void ax88796RetreivePacketData(unsigned char *localBuffer, unsigned int length);
    00196 void ax88796EndPacketRetreive(void);
    00197
    00198 // Processes AX88796 interrupts.
    00199 // Currently, this function looks only for a receive overflow condition.
    00200 // The function need not be called in response to an interrupt,
    00201 // but can be executed just before checking the receive buffer for incoming packets.
    00202 void ax88796ProcessInterrupt(void);
    00203
    00204 // execute procedure for recovering from a receive overflow
    00205 // this should be done when the receive memory fills up with packets
    00206 void ax88796ReceiveOverflowRecover(void);
    00207
    00208 // Write MII Registers
    00209 void ax88796WriteMii(unsigned char phyad,unsigned char regad,unsigned int mii_data);
    00210 // Read MII Registers
    00211 unsigned int ax88796ReadMii(unsigned char phyad,unsigned char regad);
    00212
    00213 // formatted print of all important AX88796 registers
    00214 void ax88796RegDump(void);
    00215 // formatted print of all important AX88796 PHY registers
    00216 void ax88796PhyDump(void);
    00217
    00218 #endif
    00219 //@}