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processor.h

00001 /*! \file processor.h \brief ADuC7000 Processor Initialization and Support. */
00002 //*****************************************************************************
00003 //
00004 // File Name    : 'processor.h'
00005 // Title        : ADuC7000 Processor Initialization and Support
00006 // Author       : Pascal Stang - Copyright (C) 2006
00007 // Created      : 2006.01.30
00008 // Revised      : 2006.02.20
00009 // Version      : 0.1
00010 // Target MCU   : ARM processors
00011 // Editor Tabs  : 4
00012 //
00013 // NOTE: This code is currently below version 1.0, and therefore is considered
00014 // to be lacking in some functionality or documentation, or may not be fully
00015 // tested.  Nonetheless, you can expect most functions to work.
00016 //
00017 /// \ingroup driver_arm_aduc7000
00018 /// \defgroup processor_aduc7000 ADuC7000 Processor Initialization and Support (armlib/arch/aduc7000/processor.c)
00019 /// \code #include "processor.h" \endcode
00020 /// \par Overview
00021 ///     To be written...
00022 //
00023 //*****************************************************************************
00024 //@{
00025 
00026 #ifndef PROCESSOR_H
00027 #define PROCESSOR_H
00028 
00029 // masks for use with enable/disable ARM core interrupts
00030 #define CPSR_MASK_IRQ 0x00000080
00031 #define CPSR_MASK_FIQ 0x00000040
00032 #define CPSR_MASK_INT (CPSR_MASK_IRQ | CPSR_MASK_FIQ)
00033 
00034 // general processor functions
00035 void processorInit(void);
00036 unsigned int processorEnableInt(unsigned int cpsr_mask);
00037 unsigned int processorDisableInt(unsigned int cpsr_mask);
00038 unsigned int processorRestoreInt(unsigned int cpsr_orig);
00039 
00040 
00041 // Macro for use upon entry to naked interrupt handler
00042 // - saves non-banked CPU registers and SPSR onto IRQ/FIQ stack
00043 #define ISR_ENTRY() asm volatile(" sub   lr, lr,#4\n" \
00044                                  " stmfd sp!,{r0-r12,lr}\n" \
00045                                  " mrs   r1, spsr\n" \
00046                                  " stmfd sp!,{r1}")
00047 
00048 // Macro for use upon exit from naked interrupt handler
00049 // - restores SPSR and non-banked CPU registers from IRQ/FIQ stack
00050 #define ISR_EXIT()  asm volatile(" ldmfd sp!,{r1}\n" \
00051                                  " msr   spsr_c,r1\n" \
00052                                  " ldmfd sp!,{r0-r12,pc}^")
00053 
00054 #endif
00055 //@}

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