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00022 #ifndef AD9854_H
00023 #define AD9854_H
00024
00025 #include "global.h"
00026
00027
00028
00029
00030
00031 #define AD9854_REFCLK_FREQ 50000000l
00032 #define AD9854_IO_UPDATE P04
00033 #define AD9854_RESET P05
00034
00035
00036
00037 #define AD9854_REG_BASE 0x81000400
00038
00039
00040 #define AD9854_REG_PHASE1H 0x00
00041 #define AD9854_REG_PHASE1L 0x01
00042
00043 #define AD9854_REG_PHASE2H 0x02
00044 #define AD9854_REG_PHASE2L 0x03
00045
00046 #define AD9854_REG_FREQ15 0x04
00047 #define AD9854_REG_FREQ14 0x05
00048 #define AD9854_REG_FREQ13 0x06
00049 #define AD9854_REG_FREQ12 0x07
00050 #define AD9854_REG_FREQ11 0x08
00051 #define AD9854_REG_FREQ10 0x09
00052
00053 #define AD9854_REG_FREQ25 0x0A
00054 #define AD9854_REG_FREQ24 0x0B
00055 #define AD9854_REG_FREQ23 0x0C
00056 #define AD9854_REG_FREQ22 0x0D
00057 #define AD9854_REG_FREQ21 0x0E
00058 #define AD9854_REG_FREQ20 0x0F
00059
00060 #define AD9854_REG_DELTA5 0x10
00061 #define AD9854_REG_DELTA4 0x11
00062 #define AD9854_REG_DELTA3 0x12
00063 #define AD9854_REG_DELTA2 0x13
00064 #define AD9854_REG_DELTA1 0x14
00065 #define AD9854_REG_DELTA0 0x15
00066
00067 #define AD9854_REG_UPDCLOCK3 0x16
00068 #define AD9854_REG_UPDCLOCK2 0x17
00069 #define AD9854_REG_UPDCLOCK1 0x18
00070 #define AD9854_REG_UPDCLOCK0 0x19
00071
00072 #define AD9854_REG_RAMPCLOCK2 0x1A
00073 #define AD9854_REG_RAMPCLOCK1 0x1B
00074 #define AD9854_REG_RAMPCLOCK0 0x1C
00075
00076 #define AD9854_REG_CTRL3 0x1D
00077 #define AD9854_REG_CTRL2 0x1E
00078 #define AD9854_REG_CTRL1 0x1F
00079 #define AD9854_REG_CTRL0 0x20
00080
00081 #define AD9854_REG_AMPLIH 0x21
00082 #define AD9854_REG_AMPLIL 0x22
00083
00084 #define AD9854_REG_AMPLQH 0x23
00085 #define AD9854_REG_AMPLQL 0x24
00086
00087 #define AD9854_REG_OSKEYRAMP 0x25
00088
00089 #define AD9854_REG_QDACH 0x26
00090 #define AD9854_REG_QDACL 0x27
00091
00092
00093 #define AD9854_MODE_SINGLE 0x00
00094 #define AD9854_MODE_FSK 0x01
00095 #define AD9854_MODE_RAMPFSK 0x02
00096 #define AD9854_MODE_CHIRP 0x03
00097 #define AD9854_MODE_BPSK 0x04
00098
00099
00100 #define AD9854_INVSINC_BYPASS BIT(6)
00101
00102 #define AD9854_INT_IO_UPDATE BIT(8)
00103 #define AD9854_MODE_MASK 0x00000E00
00104 #define AD9854_MODE0 BIT(9)
00105 #define AD9854_MODE1 BIT(10)
00106 #define AD9854_MODE2 BIT(11)
00107
00108 #define AD9854_TRIANGLE BIT(13)
00109 #define AD9854_CLR_ACC2 BIT(14)
00110 #define AD9854_CLR_ACC1 BIT(15)
00111
00112 #define AD9854_PLL_MULT_MASK 0x001F0000
00113 #define AD9854_PLL_MULT0 BIT(16)
00114 #define AD9854_PLL_MULT1 BIT(17)
00115 #define AD9854_PLL_MULT2 BIT(18)
00116 #define AD9854_PLL_MULT3 BIT(19)
00117 #define AD9854_PLL_MULT4 BIT(20)
00118 #define AD9854_PLL_BYPASS BIT(21)
00119 #define AD9854_PLL_RANGE BIT(22)
00120 #define AD9854_PD_DIG BIT(24)
00121 #define AD9854_PD_DAC BIT(25)
00122 #define AD9854_PD_QDAC BIT(26)
00123 #define AD9854_PD_COMP BIT(28)
00124
00125 void ad9854Init(void);
00126 void ad9854SetupIOUpdate(int state);
00127 void ad9854ClockIOUpdate(void);
00128
00129 void ad9854WritePhase1(u16 phase);
00130 void ad9854WritePhase2(u16 phase);
00131 void ad9854WriteFreq1(u64 freq);
00132 void ad9854WriteFreq2(u64 freq);
00133 void ad9854WriteDeltaFreq(u64 freq);
00134 void ad9854WriteUpdateClock(u32 updclock);
00135 void ad9854WriteRampRateClock(u32 rampclock);
00136 void ad9854WriteControlReg(u32 cr);
00137 void ad9854WriteAmplitudeI(u16 ampi);
00138 void ad9854WriteAmplitudeQ(u16 ampq);
00139 void ad9854WriteOSKeyRampRate(u16 ramprate);
00140 void ad9854WriteQDAC(u16 qdac);
00141
00142 u32 ad9854ReadControlReg(void);
00143 void ad9854ControlClear(u32 cr_clear);
00144 void ad9854ControlSet(u32 cr_set);
00145
00146
00147 void ad9854SetMode(int mode);
00148 void ad9854SetPLL(int enabled, int mult);
00149
00150 void ad9854SetFreq1(u32 freqHz);
00151 void ad9854SetUpdateClock(u32 updclockHz);
00152
00153 void ad9854ShowRegisters(void);
00154
00155
00156 #endif