00001 /*! \file ax88796conf.h \brief ASIX AX88796 Ethernet Interface Driver Configuration. */ 00002 //***************************************************************************** 00003 // 00004 // File Name : 'ax88796conf.h' 00005 // Title : ASIX AX88796 Ethernet Interface Driver Configuration 00006 // Author : Pascal Stang 00007 // Created : 10/22/2002 00008 // Revised : 8/22/2005 00009 // Version : 0.1 00010 // Target MCU : Atmel AVR series 00011 // Editor Tabs : 4 00012 // 00013 // Description : This driver provides initialization and transmit/receive 00014 // functions for the ASIX AX88796 10/100Mb Ethernet Controller and PHY. 00015 // 00016 // This code is distributed under the GNU Public License 00017 // which can be found at http://www.gnu.org/licenses/gpl.txt 00018 // 00019 //***************************************************************************** 00020 00021 #ifndef AX88796CONF_H 00022 #define AX88796CONF_H 00023 00024 // This driver supports an AX88796 connected in memory-mapped or direct I/O mode. 00025 // 00026 #define GENERAL_IO 0 00027 // Direct I/O mode assumes the AX88796 address, data, and control lines are 00028 // connected directly to processor I/O pins. The memory-bus accesses are 00029 // software emulated. 00030 // 00031 #define MEMORY_MAPPED 1 00032 // Memory-mapped mode assumes that the AX88796 is connected the processor via 00033 // the external memory bus, and that the AX88796 address space starts at the 00034 // memory location AX88796_MEMORY_MAPPED_OFFSET. 00035 // 00036 // In either mode, a seperate I/O pins is required for control of the AX88796's 00037 // hardware RESET line. 00038 00039 // set the connection type used to communicate with the NIC 00040 #define NIC_CONNECTION GENERAL_IO 00041 00042 00043 #if NIC_CONNECTION != GENERAL_IO 00044 // NIC is memory-mapped starting at this address 00045 #define AX88796_MEMORY_MAPPED_OFFSET 0x2000 00046 #else // NIC Interface through General I/O 00047 // AX88796 address port 00048 #define AX88796_ADDRESS_PORT PORTB 00049 #define AX88796_ADDRESS_DDR DDRB 00050 #define AX88796_ADDRESS_MASK 0x1F 00051 // AX88796 data port 00052 #define AX88796_DATA_PORT PORTA 00053 #define AX88796_DATA_DDR DDRA 00054 #define AX88796_DATA_PIN PINA 00055 // AX88796 control port 00056 #define AX88796_CONTROL_PORT PORTD 00057 #define AX88796_CONTROL_DDR DDRD 00058 #define AX88796_CONTROL_READPIN PD5 00059 #define AX88796_CONTROL_WRITEPIN PD4 00060 #endif 00061 00062 // AX88796 RESET pin 00063 #define AX88796_RESET_PORT PORTD 00064 #define AX88796_RESET_DDR DDRD 00065 #define AX88796_RESET_PIN PD6 00066 00067 // MAC address for this interface 00068 #ifdef ETHADDR0 00069 #define AX88796_MAC0 ETHADDR0 00070 #define AX88796_MAC1 ETHADDR1 00071 #define AX88796_MAC2 ETHADDR2 00072 #define AX88796_MAC3 ETHADDR3 00073 #define AX88796_MAC4 ETHADDR4 00074 #define AX88796_MAC5 ETHADDR5 00075 #else 00076 #define AX88796_MAC0 '0' 00077 #define AX88796_MAC1 'F' 00078 #define AX88796_MAC2 'F' 00079 #define AX88796_MAC3 'I' 00080 #define AX88796_MAC4 'C' 00081 #define AX88796_MAC5 'E' 00082 #endif 00083 00084 #endif