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Defines |
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#define | GENERAL_IO 0 |
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#define | MEMORY_MAPPED 1 |
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#define | NIC_CONNECTION GENERAL_IO |
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#define | AX88796_ADDRESS_PORT PORTB |
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#define | AX88796_ADDRESS_DDR DDRB |
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#define | AX88796_ADDRESS_MASK 0x1F |
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#define | AX88796_DATA_PORT PORTA |
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#define | AX88796_DATA_DDR DDRA |
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#define | AX88796_DATA_PIN PINA |
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#define | AX88796_CONTROL_PORT PORTD |
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#define | AX88796_CONTROL_DDR DDRD |
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#define | AX88796_CONTROL_READPIN PD5 |
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#define | AX88796_CONTROL_WRITEPIN PD4 |
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#define | AX88796_RESET_PORT PORTD |
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#define | AX88796_RESET_DDR DDRD |
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#define | AX88796_RESET_PIN PD6 |
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#define | AX88796_MAC0 '0' |
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#define | AX88796_MAC1 'F' |
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#define | AX88796_MAC2 'F' |
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#define | AX88796_MAC3 'I' |
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#define | AX88796_MAC4 'C' |
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#define | AX88796_MAC5 'E' |
