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00020 #ifndef PRISM2CONF_H
00021 #define PRISM2CONF_H
00022
00023
00024
00025 #define GENERAL_IO 0
00026
00027
00028
00029
00030 #define MEMORY_MAPPED 1
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040 #define NIC_CONNECTION GENERAL_IO
00041
00042 #if NIC_CONNECTION != GENERAL_IO
00043
00044 #define PRISM2_MEMORY_MAPPED_OFFSET 0x8000
00045 #else // NIC Interface through General I/O
00046
00047 #define PRISM2_ADDRESS_PORT PORTA
00048 #define PRISM2_ADDRESS_DDR DDRA
00049 #define PRISM2_ADDRESS_MASK 0xFF
00050
00051 #define PRISM2_HADDRESS_PORT PORTF
00052 #define PRISM2_HADDRESS_DDR DDRF
00053 #define PRISM2_HADDRESS_MASK 0x07
00054
00055 #define PRISM2_DATA_PORT PORTC
00056 #define PRISM2_DATA_DDR DDRC
00057 #define PRISM2_DATA_PIN PINC
00058
00059 #define PRISM2_CONTROL_PORT PORTG
00060 #define PRISM2_CONTROL_DDR DDRG
00061 #define PRISM2_CONTROL_IORD 1
00062 #define PRISM2_CONTROL_IOWR 2
00063 #define PRISM2_CONTROL_MEMRD 0
00064 #define PRISM2_CONTROL_MEMWR 3
00065
00066
00067
00068 #define PRISM2_MEM_ACCESS_DELAY delay_us(12)
00069 #define PRISM2_IO_ACCESS_DELAY { nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); }
00070
00071 #endif
00072
00073
00074 #define PRISM2_RESET_PORT PORTG
00075 #define PRISM2_RESET_DDR DDRG
00076 #define PRISM2_RESET_PIN 4
00077
00078
00079
00080
00081 #ifdef ETHADDR0
00082 #define PRISM2_MAC0 ETHADDR0
00083 #define PRISM2_MAC1 ETHADDR1
00084 #define PRISM2_MAC2 ETHADDR2
00085 #define PRISM2_MAC3 ETHADDR3
00086 #define PRISM2_MAC4 ETHADDR4
00087 #define PRISM2_MAC5 ETHADDR5
00088 #else
00089 #define PRISM2_MAC0 '0'
00090 #define PRISM2_MAC1 'F'
00091 #define PRISM2_MAC2 'F'
00092 #define PRISM2_MAC3 'I'
00093 #define PRISM2_MAC4 'C'
00094 #define PRISM2_MAC5 'E'
00095 #endif
00096
00097 #endif