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Defines |
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#define | GENERAL_IO 0 |
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#define | MEMORY_MAPPED 1 |
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#define | NIC_CONNECTION GENERAL_IO |
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#define | PRISM2_ADDRESS_PORT PORTA |
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#define | PRISM2_ADDRESS_DDR DDRA |
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#define | PRISM2_ADDRESS_MASK 0xFF |
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#define | PRISM2_HADDRESS_PORT PORTF |
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#define | PRISM2_HADDRESS_DDR DDRF |
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#define | PRISM2_HADDRESS_MASK 0x07 |
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#define | PRISM2_DATA_PORT PORTC |
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#define | PRISM2_DATA_DDR DDRC |
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#define | PRISM2_DATA_PIN PINC |
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#define | PRISM2_CONTROL_PORT PORTG |
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#define | PRISM2_CONTROL_DDR DDRG |
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#define | PRISM2_CONTROL_IORD 1 |
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#define | PRISM2_CONTROL_IOWR 2 |
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#define | PRISM2_CONTROL_MEMRD 0 |
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#define | PRISM2_CONTROL_MEMWR 3 |
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#define | PRISM2_MEM_ACCESS_DELAY delay_us(12) |
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#define | PRISM2_IO_ACCESS_DELAY { nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); } |
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#define | PRISM2_RESET_PORT PORTG |
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#define | PRISM2_RESET_DDR DDRG |
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#define | PRISM2_RESET_PIN 4 |
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#define | PRISM2_MAC0 '0' |
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#define | PRISM2_MAC1 'F' |
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#define | PRISM2_MAC2 'F' |
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#define | PRISM2_MAC3 'I' |
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#define | PRISM2_MAC4 'C' |
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#define | PRISM2_MAC5 'E' |
